Capstone Design Project: Modern Digital System Design
Credits:3
Grad Meth:
Reg
Prerequisite: ENEE 350.
A real-world digital system design experience that prepares students for careers in FPGA and ASIC design. Student teams use the Verilog hardware description language together with industry-standard simulation and synthesis tools to design medium-complexity digital chips that are ultimately configured and tested on FPGAs with real-world applications. Results from these projects will be presented through in-class presentations and written reports.